Up until now, power supply selection has been implemented by one of two methods. FIG. 1 shows power supply selection (circuit 102) using low threshold NMOS transistors 106, 112 in diode configuration. Output C 114 may be connected to power supply A 104, if supply voltage VA is larger than supply voltage VB supplied by power supply B 108, and voltage VC at output C 114 equals VA−VGS1. Output C 114 may be connected to power supply B 108, if supply voltage VB is larger than supply voltage VA supplied by power supply A 104, and voltage VC at output C 114 equals VB−VGS2. The voltage drop VGS is the sum of the threshold voltage VTH and the on voltage VON of a NMOS diode. VTH increases with VA or VB due to the body effect. VON increases with the diode current ID1 from power supply A to C or ID2 from power supply B to C. The power dissipation in a diode equals to VGS1×ID1 or VGS2×ID2. The supply voltage available at output C may be reduced by the voltage drop VGS which cannot be tolerated in low supply voltage designs, e.g. as may be the case in the field of chip cards. Furthermore, VGS is dependent on supply voltage, current consumption and device variation over process and temperature. If the voltage difference between power supply A 104 and B 108 approaches zero, output C is supplied by power supply A 108 as well as power supply B 108. If the diode length is decreased (in terms of reducing circuit area consumption), the leakage current, e.g. from power supply A 104 to power supply B 108, or e.g. from power supply B 108 to power supply A 104 increases significantly. Furthermore, the power VGS×ID is dissipated in the selection circuit 102.
FIG. 2 shows power supply selection (circuit 202) using cross coupled PMOS switches. Output C 214 may be connected to power supply A 204, if supply voltage VA supplied by power supply A 204 is larger than the sum of supply voltage VB supplied by power supply B 208 and threshold voltage VTH1 of PMOS switch P1 206. Voltage VC at output C 214 equals VA−VDS1. Output C 214 may be connected to power supply B 208, if supply voltage VB supplied by power supply B 208 is larger than the sum of supply voltage VA supplied by power supply A 204 and threshold voltage VTH2 of PMOS switch P2 212. Voltage VC at output C 214 equals VB−VDS2. The drain to source voltage drop VDS at a PMOS switch, e.g. 206, 212, is much smaller than the gate to source voltage drop VGS at a NMOS diode e.g. 106, 112, in FIG. 1. Therefore the power dissipation in the circuit may be significantly reduced in comparison to FIG. 1. However, the overdrive voltage VO of a PMOS switch, e.g. 206, 212, equals VA−VB−VTH (in other words VO=VA−VB−VTH) and is therefore dependent on the voltage difference between power supply A 204 and power supply B 208. The voltage drop VDS at a PMOS switch, e.g. 206, 212, may be dependent on VO and may increase significantly if the voltage difference between VA and VB becomes smaller. If the voltage difference between power supply A 204 and power supply B 208 becomes smaller than or equal to VTH, output C may be neither connected to power supply A nor to power supply B. Therefore output C may be floating.